The present invention relates to an improvement in a word line drive circuit for a random access memory employing field effect transistors.
FIG. 1 shows a part of a prior art random access memory (hereinafter referred to as RAM), having memory cells arranged in rows and columns to form a matrix. The memory cells in the same column are connected to a common bit line which transmits data read from or written into the memory cells connected thereto. The memory cells in the same row are connected to a common word line which transmits a signal for controlling a switching field effect transistor (hereinafter referred to to as FET) provided within each of the memory cells connected thereto.
Each of the memory cells, such as 1a through 1d stores one bit data of a logical "1" or a logical "0" (hereinafter simply referrerd to as "1" or "0"). Each of the memory cells comprises a storage capacitor 2 with one electrode grounded, and a switching FET 3 with one main electrode connected to the other electrode of the storage capacitor 2. The storage capacitor 2 contains data of "1" or "0", and the switching FET 3 is used for reading, writing or holding data from or in the storage capacitor 2. The other main electrode of the switching FET 3 is connected to one of the bit lines 4, 6, etc. (only 4 and 6 being illustrated), which transmits data for the memory cells. The gate of the switching FET 3 is connected to one of the word lines 5, 7, etc. (only 5 and 7 being illustrated), which transmits a signal for controlling ON/OFF operation of the switching FET 3. A decoder 8 decodes address signals Ax.sub.1 , Ax.sub.1, - - - Ax.sub.n, Ax.sub.n (hereinafter generalized as Ax, Ax) provided through terminals 9, and supplies a voltage to one of output lines 10, 11, etc. (only 10 and 11 being illustrated). FETs 12, 13, etc. (only 12 and 13 being illustrated) connect the word lines 5, 7, etc. (only 5 and 7 being illustrated) with a terminal 14, depending on the voltaghe levels on the output lines 10, 11, etc. respectively. On the terminal 14, a word line drive signal .phi.w is provided. A terminal 15 is an input terminal for a clock signal .phi.RAS. In the following description, it is assumed that there are only four memory cells 1a through 1d, two word lines and two bit lines.
FIG. 2 is a timing chart illustrating read operation of the circuit shown in FIG. 1. Here, it is assumed that data "0" is read from the memory cell 1a. In FIG. 2, the period from the time t0 to the time t1 is a precharge period, and in this period the output line 10 and 11 of the decoder 8 are precharged to be "1" by an internal clock signal .phi.RAS which is in phase with an external clock signal RAS (Row Address Strobe). During this precharge period, a voltage V5 on the word line 5 and a voltage V7 on the word line 7 are at "0", because the word line drive signal .phi.w is at "0". At the time t1, the clock .phi.RAS becomes "0", after which external address signals are taken in. Then, at the time t2, internal address signals Ax, Ax are inputted to the decoder 8. Supposing that the word line 5 is selected, for example, the voltage level on the node 11 is turned to "0", while the voltage level on the node 10 is kept at "1". At the time t3, the word line drive signal .phi.w is turned from "0" to "1", and this signal is transmitted to the word line 5 through the FET 12, which is conductive due to the node 10 being at "1", so that the voltage on the word line 5 is turned from "0" to "1". As a result, the FETs 3 in the memory cells 1a and 1b are turned on, so that data in the memory cells 1a and 1b are read out on to the bit lines 4 and 6. Reading data on to a bit line causes a minute voltage change on the bit line. After that, at the time t4, the minute voltage change is amplified by an amplifier circuit (not shown) connected to the same bit line.
To increase the speed of the reading from the memory cells, a voltage supplied to the word lines is usually set higher than a power supply voltage for the circuit. Raising the voltage on the word lines is effective because it lowers the ON resistance of the FETs 3.
FIG. 3 shows an example of a word line drive circuit in which a voltage higher than a power supply voltage is supplied to word lines, which comprises a signal generator 20 producing a word line drive signal .phi.w, a signal generator 21 producing a boosting signal .phi.p, a boosting capaciter 22 which is connected between the output terminal 14 for the word line drive signal .phi.w and the output terminal 23 for the boosting signal .phi.p, and a parasitic capacitance element 24 between the output terminal 14 and the ground.
FIG. 4 is a timing chart illustrating operation of the circuit shown in FIG. 3. The output terminal 14 in FIG. 3 corresponds to the terminal 14 in FIG. 1 and the drive signal .phi.w is transmitted to the word line 5. After the drive signal .phi.w increases from "0" to "1" at the time t2, the boosting signal .phi.p increases from "0" to "1" at the time t2', so that the voltage level of the signal .phi.w increases to a value Vp higher than V because of the boosting capacitor 22. The voltage increment .DELTA.V is given by EQU .DELTA.V={C22/(C22+C24)}V,
where C22 and C24 are capacitances of the capacitors 22 and 24, respectively.
However, the word line drive circuit described above has the following problem. As illustrated in FIG. 4, the drive signal .phi.w is increased from "0" to "Vp". But, the increasing curve is not smooth and has a step at the time t2'. The decrease of the ON resistance of the FET 3 is in step with this curve, so that the speed of reading data from a memory cell is not high enough for certain applications. Although the increasing curve of .phi.w can be smoothed by advancing the rising time t2' of the signal .phi.p, this lowers the ultimate voltage Vp because the boosting is started when .phi.w is still low. As a result, reading speed is limited.